Digital wx radar receiver design based on highly efficient bandpass sampling FPGA architecture

As digital electronics become faster and more efficient, it becomes possible to move the analog/digital interface in a radar down-conversion system further towards the antenna. Taking full advantage of this opportunity will result in a more highly integrated and reconfigurable design. By removing unnecessary analog components, the error from component variability and noise injected into the signal of interest is reduced, the size of the receiver and the power required for operation is minimized, and the overall cost of the system can be lowered. This research program is focused on creating a low-cost digital radar receiver at the University of Oklahoma. Successful testing of this new receiver has occurred on the phased array antenna at the National Weather Radar Testbed (NWRT) in Norman, Oklahoma. The low-cost, compact receiver is available for use in other radar projects as a way of obviating the need for commercial radar receivers, which can be many times more expensive and non-flexible. One such use is in the Atmospheric Imaging Radar, which is planned to use twenty-four digital receiver channels so that radar beam-forming can be done in post-processing.

Building on previous work with a single-channel receiver, this study aims to expand the design for more capabilities. Through the utilization of a low-power, simultaneous- sampling eight-channel ADC with high-speed serial data links and a cost-efficient FPGA with integrated DSP slices, eight data channels can be digitized, processed and transferred at the same time in one compact receiver unit. An ethernet interface has been included which allows for a scalable control channel so that the digital receiver's operations such as filter coefficients or ADC sampling parameters can be modified. This also makes it possible to change the firmware of the FPGA in seconds, without the need for physical access. Finally, this research also focuses on the construction of a computer to store and process the 160 MB/sec of data output from the digital receiver.