87th AMS Annual Meeting

Wednesday, 17 January 2007: 2:00 PM
Preliminary Multifunction Phased Array Radar (MPAR) Preprototype Development
217A (Henry B. Gonzalez Convention Center)
Jeffrey Herd, MIT Lincoln Laboratory, Lexington, MA; and S. Duffy, M. Vai, F. Willwerth, and L. Retherford
This paper describes initial work developing a scaled “pre-prototype” MPAR array that incorporates the critical MPAR technologies described by Weber et al. (2007). This design work is providing technical and cost details that can be used to evaluate the viability of the MPAR concept.

The pre-prototype active, electronically-scanned array will be 4.2 m in diameter, providing sufficient radiated power, antenna gain and angular resolution (2.0° pencil beam) to demonstrate key weather and aircraft surveillance functions. The array will radiate and receive in two 1 MHz sub-bands, and will utilize a 1-dimensional, 16 channel overlapped subarray beamformer to digitally form two independent vertical clusters of 8 receive beams, one for each sub-band. A brick module design is utilized with the major RF subsystems in a 6U Eurocard chassis behind the radiating elements. The dual channel TR-element design incorporates low-cost COTS components and a custom-designed phase shifter to maintain the total parts cost at less than $20 per TR-element. Key to maintaining low TR-element cost is the use of a modest peak power (1 to 10 W) COTS high power amplifier. The overlapped subarray beamformer will initially be implemented using a multilayer printed circuit board (PCB) design based on Lincoln Laboratory's X-band Space and Airborne Radar Transformational Array (SPARTA) program (Herd et al., 2005). It is anticipated that the current Laboratory efforts to develop an RFIC based overlapped subarray beamformer will significantly reduce the costs of this MPAR subsystem relative to the PCB design. The subarray output receiver design is derived from the Lincoln Digital Array Radar (DAR) program (Rabideau et al, 2003) and provides high performance at a modest cost. A scalable, high performance digital beamformer preliminary design is described. Workable COTS implementation technologies include FPGA, ASIC, Multichip Module (MCM) and mixed signal designs.

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