Tuesday, 8 January 2019: 3:30 PM
North 128AB (Phoenix Convention Center - West and North Buildings)
Handout (2.7 MB)
Since 2007, MIT Lincoln Laboratory (LL) has been developing low-cost phased array panel technology in support of the Multifunction Phased Array Radar (MPAR) program. Over the last decade, LL has teamed with MACOM to develop an S-band, 64-element dual-polarization (pol) panel with a peak radiated power of 6W per element per pol. The 3rd generation design of this panel has been used to populate the MPAR Advanced Technology Demonstrator (ATD), a 4m-diameter, 76-panel, fully polarimetric AESA radar. LL completed calibration and testing of the ATD at the nearfield chamber test facility in Lexington, MA in May of 2018, and deployed the system to the National Weather Radar Testbed (NWRT) at the National Severe Storm Laboratory (NSSL) in Norman, OK. Initial Operating Capability (IOC) is scheduled for mid-2019.
LL is currently researching the next step in performance and capability for low-cost panel technology: a large bandwidth, high power, element-level digital array. Element-level digital arrays offer several advantages over analog arrays, including better dynamic range, more flexibility in beamforming, and higher precision calibration. The system proposed by LL is enabled by recent technology developments including high power Gallium Nitride (GaN) amplifiers, low-profile liquid cooling, and Xilinx’s RF System-on-Chip (RFSoC), a highly-integrated module that combines multiple channels of RF-sampling ADC’s/DAC’s with a high-performance Field-Programmable Gate Array (FPGA). This paper discusses the motivations, key enabling technologies, and preliminary design for the proposed system.
LL is currently researching the next step in performance and capability for low-cost panel technology: a large bandwidth, high power, element-level digital array. Element-level digital arrays offer several advantages over analog arrays, including better dynamic range, more flexibility in beamforming, and higher precision calibration. The system proposed by LL is enabled by recent technology developments including high power Gallium Nitride (GaN) amplifiers, low-profile liquid cooling, and Xilinx’s RF System-on-Chip (RFSoC), a highly-integrated module that combines multiple channels of RF-sampling ADC’s/DAC’s with a high-performance Field-Programmable Gate Array (FPGA). This paper discusses the motivations, key enabling technologies, and preliminary design for the proposed system.
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