Session 8B.3 A generic radar processor design using Software Defined Radio

Wednesday, 8 August 2007: 11:00 AM
Meeting Room 2 (Cairns Convention Center)
Tom Brimeyer, NCAR, Boulder, CO; and C. Martin, E. Loew, G. Farquharson, S. Khatri, and S. Paul

Presentation PDF (173.1 kB)

Supporting the design and upgrade efforts for radar signal processors over a wide array of radar platforms can easily exhaust available resources. Commercially available Software Defined Radio boards containing front end IF digitization and Field Programmable Gate Array (FPGA) technology can provide the framework and flexibility to design generic signal processors. These boards accept IF radar data which are then digitized before being filtered and demodulated in the FPGA to produce raw in-phase and quadrature-phase (IQ) data. The raw IQ data can be further processed by the FPGA or can be sent, as is, to the host PC for spectral or pulse pair processing. By judiciously choosing the processing architecture implemented in the FPGA, a wide range of radar IF's and gate spacings can be accommodated using the same design; hence, the term generic.

This paper will discuss the generic architecture of a radar signal processor from the IF digitization to the output of IQ data for post processing. It will also cover the design of programmable components such as filters, oscillators, and decimators that will fit the needs of multiple radar platforms. The redesign of the ELDORA radar signal processor will also be looked at as an example of what post processing can take place within the FPGA itself.

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