3.3 Road-Testing Intel's Knights Landing Processor for Global NWP

Thursday, 26 January 2017: 11:00 AM
Conference Center: Chelan 2 (Washington State Convention Center )
John Michalakes, UCAR/NRL, Monterey, CA; and A. Mueller

Xeon Phi Knights Landing (KNL), Intel’s newest Many Integrated Core (MIC) processor has the potential for very high (peak 3 TF/s) double precision floating point performance in a 200 watt package, offering a path to exascale if global NWP models can use KNL efficiently. NWP applications must expose at least thousand-way parallelism through threads and vectorization with sufficient computational intensity to overcome memory system bottlenecks.  The NEPTUNE/NUMA spectral element dynamical core is more expensive in in terms of floating point operations its current state compared to finite-volume models. However, NEPTUNE/NUMA has ample parallelism and the potential for superior memory locality that will allow it to scale to very high (3km and finer) real time global NWP domains. We will present detailed computational and memory system measurements using NEPTUNE/NUMA to investigate capabilities of and optimization strategies for next-generation global NWP models on KNL.
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