Handout (4.1 MB)
For many years, Ethernet and PCIe have been two well-known data link protocols solution for connecting processors together in system. As the increasing demand for bandwidth and complexity of systems, those two protocols have significant limitations in transmission latency and topology. Thus a more flexible and efficient fabric interconnects technology, RapidIO, has become more and more popular. In general, RapidIO shares similar physical layer as Ethernet while achieves better data transaction performance and more flexible system architecture than PCIe and Ethernet protocols. Even with these advanced data link technologies, the large communication bandwidth is still a tremendous challenge. In order to further reduce the data stream rate without loss of information, we propose to incorporate compressive sampling (CS) concept into the MPAR backend system.
Attention has been focused on the following issues: (1) Robustness of signal recovery from noisy array channel data, especially for the received signals before pulse compression. (2) Recovery computing time and resources overhead, and whether it can fit in a digital receiver's front-end, (3) How the efficient data transportation support the overall backend computing scheme in term of meeting the NSWRC functionality requirements.
A small-scale DSP-based computing testbed is established to verify the CS channel compression concept and emulate end-to-end computing latency. Firstly, Matlab simulations has been performed for both discrete targets and distributed targets. The simulated data is downloaded to the computing platform, and real-time pulse compression, Doppler processing as well as beamforming are implemented. The channel performance and overall latency with and without CS is compared.